In the recent years, memories are becoming ubiquitous and commonly used in various electronic devices, such as personal computers, laptop computers, smart phones, tablets, digital cameras, and etc. In order to increase memory density, memory designs have used three-dimensional (3D) architectures. A 3D memory includes more memory cells than a two-dimensional (2D) memory. As the number of memory cells increases, the number of signal lines, e.g. bit lines and/or word lines, increases accordingly.
The radius of upper layers of a 3D memory may be greater than the radius of lower layers of the 3D memory, taking a substrate of the 3D memory as a bottommost layer, and thus in an erase-verify operation, the effect of electric field of a erase-verify voltage applied on upper layers of the 3D memory is different from the effect of electric field of the erase-verify voltages applied on lower layers of the 3D memory. In addition, residual charges would result in an erase-verify failure of the erase-verify operation.
Accordingly, there is a need for an erase-verify method for a three-dimensional memory and a memory system.